This invention relates to an integrated circuit memory device, and more particularly to a sense amplifier isolation circuit layout using reduced die area over current layouts in a dynamic RAM architecture.
A dynamic random access memory (DRAM) that occupies the smallest silicon area for the largest storage capacity is preferred. Using a small silicon area permits smaller chips to be made of a high DRAM density and also permits more chips to be made on a single wafer. This reduces the cost of DRAM manufacture while at the same time increases the production.
A DRAM chip includes a number of distinct circuits such as: memory cells for storing data, sense amplifiers for reading data from the memory cell and circuits to permit data input and output to and from the memory.
Many identical copies of certain circuits, such as the memory cells and sense amplifiers, are required on a single DRAM. Even a small reduction in the area of such circuits can result in a significant reduction in overall chip area.
Some of today""s DRAMs have many hundreds or even many thousands of identical sense amplifier circuits. A modest reduction in the layout area required by a sense amplifier will thus be multiplied by the number of sense amplifiers on the chip to provide a reduction of total memory size.
Reducing the size of a sense amplifier can be somewhat difficult from an operational standpoint. In a typical DRAM memory cell, the charge difference between a high and a low is very small, typically one million electrons or even less. Consequently, the sense amplifier must be able to sense a very small differential voltage between bit line pairs BL and BL*. Maximizing the sense amplifier""s speed and reliability is important to ensure proper operation of the DRAM. If the area is reduced too much, speed and reliability both suffer. It has thus been difficult in the prior art to reduce the overall area required for a sense amplifier while maintaining the necessary speed and reliability.
A block diagram of a typical prior art DRAM integrated circuit is shown in FIG. 1. Such a memory device has a plurality of memory cells MC arranged in rows and columns and located in memory array blocks 11 and 13. Each block 11 and 13 includes a plurality of word lines WL arranged in rows, and a plurality of bit line pairs BL and BL* arranged in columns. Each memory cell MC is accessed via a word line WL and outputs data onto a bit line BL or BL*. The area adjacent the last row of memory cells MC at the edge of the block may be reserved for dummy cells or redundancy memory cells. Alternatively, the area adjacent the memory cells MC at the edge of a block may remain unused, thus representing a great sacrifice of precious die area.
As known to those skilled in the art and as shown in FIG. 1, a sense amplifier 9 is located outside memory array blocks 11 and 13. A typical prior art sense amplifier 9 includes a number of sense amplifier components 15 as well as isolation devices 17. These isolation devices 17 isolate block A from the sense amplifier 9 when reading from or writing to block B and isolate block B from the sense amplifier 9 when reading from or writing to block A, respectively. The isolation devices in prior art sense amplifiers may be full transmission gates having an NMOS transistor and a PMOS transistor. A typical sense amplifier also includes the following sense amplifier components: an equalization circuit (not shown); a bias circuit (not shown); cross-coupled amplifiers (not shown); and input/output devices (not shown). Bit line pairs 31 and 33 may be connected to sense amplifiers (not shown) at the other sides of memory blocks 11 and 13, respectively.
It would be desirable to minimize DRAM layout by minimizing the layout of sense amplifiers. As will be appreciated, the sheer number of components included in a sense amplifier, coupled with strict design rules intended to prevent the occurrence of errors, makes reduction of the sense amplifier components very difficult. For example, an active pull-up transistor in a typical sense amplifier may occupy up to six times the die area occupied by a transistor in a memory cell. Such a sense amplifier transistor is sized to match specific functions and cannot be reduced in size. Other transistors located in the sense amplifier block must be size matched as well and thus these transistors cannot be reduced in size.
The present invention reduces sense amplifier size beyond the constraints imposed by design rules in the sense amplifier, therefore saving precious die area. A layout according to the present invention relocates portions of the sense amplifier, such as the sense amplifier isolation devices, into the rows of memory cells at the edge of a memory array. Some of the circuit elements of the sense amplifiers are thus located within the densely laid out memory array block rather than within the sense amplifier circuit area, even though they are traditionally considered part of the sense amplifier circuit.
In a first embodiment of the present invention, a memory device has an array of memory cells which are positioned in a first block and a second block on either side of the sense amplifiers. The memory cells are arranged in rows and columns. A plurality of bit lines is coupled to the memory cells and a plurality of word lines is coupled to the memory cells. A row of sense amplifiers is positioned between the first block and the second block, one for each pair of bit lines and a plurality of electrical connections is made between the respective sense amplifier and the bit lines in each block. An isolation transistor is electrically connected in series between the bit lines and the rest of the circuits in the sense amplifier for that particular bit line. A plurality of isolation transistors, one for each bit line, are positioned in a row at the edge of the memory array. An isolation control signal provides a gate voltage to the isolation transistors to connect the bit lines of the respective blocks to the sense amplifiers at a selected time.
A sense amplifier layout as described above significantly reduces sense amplifier layout area, by up to 30% over prior art sense amplifier designs.
A second embodiment of the present invention uses full transmission gates, having an NMOS transistor and a PMOS transistor, as isolation transistors instead of an NMOS transistor with a boosted gate voltage. The PMOS transistor is located within the sense amplifier block area and spaced from the memory cell array, while the NMOS transistor is located within the first and second blocks of memory cell array.